Fabrication of integrated circuits (ICs) generally involves a sequence of steps intended to take a concept, such as the concept of a digital video encoder, and from it design an integrated circuit, which can be fabricated in large quantities for sale to users. These steps are, typically, (1) initial functional and behavioral design and simulation, based on the concept, (2) circuit/netlist design and simulation, based on the behavioral design, (3) mask design, auto-device generation and on-line verification, based on the netlist, to generate a GDSII database embodying the physical design of the IC, (4) design rule, electric rule and layout-versus-schematic (LVS) verification, (5) fabricating sample ICs using the GDSI database, (6) testing the sample ICs, and, finally, (7) fabricating ICs in quantity.
One problem that IC designers must address is that of substrate noise. This is noise that is generated during normal operation of the IC, typically from signal transitions on signal lines or in devices, and that is coupled through the substrate to other locations in the IC where the noise is picked up and adversely affects performance at the other locations. Optimization of IC performance frequently includes analysis and minimization of such substrate noise.
The problem of substrate noise can be particularly problematic in mixed signal IC designs. In such designs, substrate noise analysis is essential for avoiding any performance degradation or failure due to the noise coupled through the substrate from the noisy digital circuits, i.e, the digital core, to the sensitive analog circuits. It is also important to analyze mixed signal IC designs for substrate noise sensitivity early in the design cycle, so that the design teams have sufficient time to take steps to create effective on-chip electrical isolation strategy without extensive and costly re-design cycles.
In mixed signal IC design, analyzing substrate noise generally has three parts: (1) estimating the noise generated by the digital circuits, (2) characterizing the propagation of such noise through the substrate, and (3) characterizing the resulting manifestation of such noise in analog circuits, including the impact of various isolation and noise reduction techniques on the analog circuits. Such analysis in large mixed signal ICs, involving multi-million gate designs, is especially difficult.
Existing approaches for estimating noise generation in large mixed signal designs involves characterizing all the cells used in the design and creating a noise macro model for each cell. This model is then used in conjunction with the switching activity report generated during a gate level simulation to estimate the total current being injected into the substrate. However, to follow this methodology, one needs to (1) do a full library characterization, which is time consuming, and (2) have a full gate level netlist before any simulations can be done. This methodology also cannot fully account for different process technologies, for example the use of deep NWELL or deep PWELL, without doing extensive recharacterization of the library. It also cannot do a “what-if” type analysis of the effect of decoupling capacitors, unless they are included as part of the gate level netlist. Thus, for accurate substrate noise estimation for effective reduction, a significant application of design resources must be applied, adding to the cost of the IC design.